Microelectromechanical systems (MEMS) are microdevices widely used as advanced sensors, microfluidic controls, or micromachines. Advanced MEMS sensors can be found in automobiles, medical instrumentation, or process control applications, and provide accurate determinations of pressure, temperature, acceleration, gas concentration, and many other physical or chemical states. Microfluidic controls include microvalves for handling gases or liquids, flow gauges, and ink jet nozzles, while micromachines include microactuators, movable micromirror systems, tactile moving assemblies, and such devices as atomic force microscopy cantilevers. Commonly, microdevices are constructed from semiconductor material substrates such as crystalline silicon, widely available in the form of a semiconductor wafer used to produce integrated circuits.
Because of the commonality of material, fabrication of microdevices from a semiconductor wafer substrate can take advantage of the extensive experience in both surface and bulk etching techniques developed by the semiconductor processing industry for integrated circuit (IC) production. Surface etching, used in IC production for defining thin surface patterns in a semiconductor wafer, can be modified to allow for sacrificial undercut etching of thin layers of semiconductor materials to create movable elements. Bulk etching, typically used in IC production when deep trenches or vias must be formed in a wafer using anisotropic etch processes, can be used to precisely machine edges or trenches in microdevices. Both surface and bulk etching of wafers can proceed with "wet processing", using chemicals such as potassium hydroxide in solution to remove non-masked material from a wafer. For microdevice construction, it is even possible to employ anisotropic wet processing techniques that rely on differential crystallographic orientations of materials, or the use of electrochemical etch stops, to define microdevice components. Unfortunately, freedom in designing complex microdevices is greatly constrained when wet processing etch techniques used. Wet processing is severely limited by dependence on semiconductor crystal orientation and the materials and etchants used. Even worse, microdevices containing thin extending structures are often susceptible to damage as a result of hydrodynamic forces incurred during wet processing.
An alternative etch processing technique that allows much greater microdevice design freedom is commonly known as "dry etch processing". This processing technique avoids many of the problems associated with wet etch processing of microdevices, and is particularly suitable for anistropic etching of fine structures. Dry etch processing encompasses many gas or plasma phase etching techniques ranging from highly anisotropic sputtering processes that bombard a wafer with high energy atoms or ions to displace wafer atoms into vapor phase (e.g. ion beam milling), to somewhat isotropic low energy plasma techniques that direct a plasma stream containing chemically reactive ions against a wafer to induce formation of volatile reaction products. Intermediate between high energy sputtering techniques and low energy plasma techniques is a particularly useful dry etch process known as reactive ion etching.
Reactive ion etching involves directing an ion containing plasma stream against a semiconductor wafer for simultaneous sputtering and plasma etching. Reactive ion etching retains some of the advantages of anisotropy associated with sputtering, while still providing reactive plasma ions for formation of vapor phase reaction products in response to contacting the reactive plasma ions with the wafer. In practice, the rate of wafer material removal is greatly enhanced relative to either sputtering techniques or low energy plasma techniques taken alone. Reactive ion etching therefore has the potential to be a superior etching process for construction of microdevices, with relatively high anistropic etching rates being sustainable.
Unfortunately for builders of microdevices, even though dry etch techniques such as reactive ion etching allow for high speed anisotropic etching of a semiconductor wafer rate, the accuracy of dry etch techniques is still not sufficient for many microdevice applications. For example, when trenches of a certain depth are to be defined in a wafer, dry etching by a reactive ion etch or other suitable technique is allowed to proceed for some empirically determined duration. This technique, known as time etch stop, presumes that all trenches will be cut to the same depth across the wafer if all etching factors are maintained as constants. For example, if the plasma stream is unvarying across the wafer, the wafer material is homogeneous and of constant thickness, and reaction products are removed at identical rates, all trenches of identical size and shape across the wafer should be cut to the same depth. However, as will be appreciated, the foregoing factors are generally not constant. Variances in the plasma stream, irregularities in the wafer thickness (typically on the order of 300 nanometers across a wafer), differences in materials or positioning, and differences in reaction removal rate will all deleteriously affect the accuracy of etching. This is particularly true when trenches vary in shape or dimensions, with large trenches generally being cut much faster than small trenches, primarily due to the reduced rate of removal of vapor phase ion reaction products from the smaller trenches. Although various expedients such as real time monitoring of etch rates have been tried, in practice it is very difficult to maintain accuracy of etch depth to within less than 300 nanometers for even adjacent structures. Accuracy of etch depth and thickness control during micromachining of widely separated structures on a wafer, or microstructures on different wafers, is typically even worse.
Accordingly, since current microdevice fabrication techniques have significant limitations, what is needed is a process for designing and constructing microdevices that is not limited by crystallographic orientation of a material or material choice, is not substantially limited in thickness, has a high reproducibility, and is compatible with existing integrated circuit fabrication processes and equipment. The process should allow a microdevice to be constructed with etch depth accuracies to within about 100 nanometers. For highest microdevice production yields, this etch depth accuracy must be maintained across a wafer substrate, and even between wafers. Further, such micromachining accuracy should be maintained regardless of feature size, with depth of small single micrometer width trenches as accurately defined as large hundred micrometer width trenches.
The present invention addresses these requirements by defining a dry etch micromachining process. Use of the process requires a substrate having at least one heterojunction between dissimilar materials. The substrate can include semiconductors (e.g. silicon, germanium, or gallium arsenide), and the dissimilar materials can include various p- or n-doped semiconductors. A voltage bias is applied across at least one heterojunction of the substrate, and an ion containing plasma is directed against the substrate to etch the substrate. Because of the applied voltage bias, etching is significantly slowed or substantially stopped when etch depth reaches the heterojunction.
In certain embodiments, the heterojunction in the substrate is formed by coextensive or patterned epitaxial growth of a n-type layer on a p-type semiconductor wafer, or alternatively, by epitaxial growth of a p-type layer on an n-type wafer. In another embodiment, a heterojunction can be formed by wafer bonding a p-type silicon wafer and a n-type silicon wafer to form a silicon substrate having a p-layer and a n-layer. The silicon substrate is positioned in a conventional dry etching device, with the n-layer facing a stream of negative chemically reactive ions such as fluorine ions in a fluorocarbon plasma. The reverse voltage bias maintained is less than about the breakdown voltage of p-n heterojunctions in silicon, typically about 50 to about 100 volts, although it may range as high as 300 volts for certain configurations. To increase anisotropic etching of the silicon wafer and reduce destruction of sidewalls, a coating cycle can be maintained throughout the etch process. An erodable protective material (e.g. a polymer coating) is periodically applied to the silicon substrate to limit sidewall damage to the n-layer while still allowing downward etching into the substrate. Alternatively, in certain embodiments it is possible to omit this coating cycle by provision of a suitably cooled (typically less than 20 degrees Celsius) substrate and proper selection of reactant species, with desired anisotropic etching rates being maintained.
Constructing microdevices in defined patterns is enabled by masking the silicon substrate with a protective patterned layer. This protective patterned layer (mask) defines a masked surface that generally will not be eroded away during processing, protecting the underlying substrate from etching. That portion of the substrate that is not masked with a protective patterned layer constitutes an etchable surface. In certain embodiments, pattern control can be extended by selective diffusion or implantation of dopants into a wafer to produce, for example, a patterned heterojunction player that is not coextensive with an overlaying n-layer. When the heterojunction is not coextensive and continuous in a wafer, downward etching completely through the substrate is possible in those patterned regions lacking an underlying heterojunction.
In one preferred embodiment, the method of the present invention can be practiced by use of a novel chuck for holding a substrate in an otherwise conventional dry etch processing apparatus. The dry etch apparatus must be suitable for micromachining a substrate having a first and a second layer of dissimilar materials joined together at a heterojunction, and can be any of the many commercially available dry etching units. In this embodiment of the invention, the chuck holding the substrate has a first electrical contact positionable to contact the first layer, and second electrical contact positionable to contact the second layer. The first and second electrical contacts are maintained in electrical isolation from each other, and a voltage source is connected to the first electrical contact of the chuck to apply a voltage potential across the heterojunction of the substrate. As those skilled in the art will appreciate, although individual electrical contacts can be employed, typically multiple electrical contacts are used to more evenly distribute the voltage bias applied across the heterojunction of the substrate.
Additional functions, objects, advantages, and features of the present invention will become apparent from consideration of the following description and drawings of preferred embodiments.